Datasheet
SAM9G20
DS60001516A-page 392 2017 Microchip Technology Inc.
29.6.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers.
This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.
29.6.3.4 Transfer Delays
Figure 29-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to
modify the transfer waveforms:
• The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register.
Allows insertion of a delay between release of one chip select and before assertion of a new one.
• The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be
delayed after the chip select has been asserted.
• The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows
insertion of a delay between two transfers occurring on the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 29-7: Programmable Delays
29.6.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before
and after each transfer.
The peripheral selection can be performed in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined
by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This
means that the peripheral selection can be defined for each new data.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data
transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register
to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written
in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode
requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the
number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal
means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any
intervention of the processor.
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK