Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 387
SAM9G20
29.3 Application Block Diagram
Figure 29-2: Application Block Diagram: Single Master/Multiple Slave Implementation
29.4 Signal Description
29.5 Product Dependencies
29.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the
PIO controllers to assign the SPI pins to their peripheral functions.
29.5.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable
the SPI clock.
29.5.3 Interrupt
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires program-
ming the AIC before configuring the SPI.
Table 29-1: Signal Description
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1–NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3