Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 353
SAM9G20
Figure 28-5: Input Glitch Filter Timing
28.4.10 Input Change Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt
is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis-
able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detec-
tion is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The
Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO
Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding
bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together
to generate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when
PIO_ISR is read must be handled.
Figure 28-6: Input Change Interrupt Timings
28.5 I/O Lines Programming Example
The programing example as shown in Table 28-1 below is used to define the following configuration.
• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor
• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change
interrupts
• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor,
no glitch filter
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles up to 2 cycles
1 cycle
1 cycle
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access