Datasheet

SAM9G20
DS60001516A-page 328  2017 Microchip Technology Inc.
27.4.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled
and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME
remains high until the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 27-9: Receiver Framing Error
27.4.3 Transmitter
27.4.3.1 Transmitter Reset, Enable and Disable
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing
the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit
Holding Register DBGU_THR before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immedi-
ately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Hold-
ing Register, the characters are completed before the transmitter is actually stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops
the transmitter, whether or not it is processing characters.
27.4.3.2 Transmit Format
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the
Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one
optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register
DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even
parity, or a fixed space or mark bit.
Figure 27-10: Character Transmission
27.4.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when
the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to
the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is com-
pleted, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding reg-
ister is empty.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit
TXEMPTY rises after the last stop bit has been completed.
D0 D1 D2 D3 D4 D5 D6 D7 PS
DRXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
D0 D1 D2 D3 D4 D5 D6 D7
DTXD
Start
Bit
Parity
Bit
Stop
Bit
Example: Parity enabled
Baud Rate
Clock