Datasheet

SAM9G20
DS60001516A-page 304  2017 Microchip Technology Inc.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore,
the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the
value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written.
An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the
same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service
routine to make sure the debugger does not modify the AIC context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
1. Calculates active interrupt (higher than current or spurious).
2. Determines and returns the vector of the active interrupt.
3. Memorizes the interrupt.
4. Pushes the current priority level onto the internal stack.
5. Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only
performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in
Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.
26.7.6 Spurious Interrupt
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of
an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur
when:
• An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.
• An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is acti-
vated for a short time. (As in the case for the Watchdog.)
• An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source.
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens,
the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of
a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow.
This handler writes in AIC_EOICR and performs a return from interrupt.
26.7.7 General Interrupt Mask
The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are
driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up
the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event
occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.