Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 299
SAM9G20
26.7.2.1 External Interrupt Edge Triggered Source
Figure 26-6: External Interrupt Edge Triggered Source
26.7.2.2 External Interrupt Level Sensitive Source
Figure 26-7: External Interrupt Level Sensitive Source
26.7.2.3 Internal Interrupt Edge Triggered Source
Figure 26-8: Internal Interrupt Edge Triggered Source
Maximum FIQ Latency = 4 Cycles
Maximum IRQ Latency = 4 Cycles
nFIQ
nIRQ
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ
MCK
nIRQ
Peripheral Interrupt
Becomes Active
Maximum IRQ Latency = 4.5 Cycles