Datasheet

SAM9G20
DS60001516A-page 298  2017 Microchip Technology Inc.
26.7.1.5 Internal Interrupt Source Input Stage
Figure 26-4: Internal Interrupt Source Input Stage
26.7.1.6 External Interrupt Source Input Stage
Figure 26-5: External Interrupt Source Input Stage
26.7.2 Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external inter-
rupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on
the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For
the standard interrupt, resynchronization times are given assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
Edge
Detector
ClearSet
Source i
AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
AIC_ISCR
AIC_ICCR
Fast Interrupt Controller
or
Priority Controller
FF
Lev
el/
Edge
AIC_SMRI
(SRCTYPE)
Edge
Detector
ClearSet
Pos./Neg.
AIC_ISCR
AIC_ICCR
Source i
FF
Level/
Edge
High/Low
AIC_SMRi
SRCTYPE
AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
Fast Interrupt Controller
or
Priority Controller