Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 297
SAM9G20
The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling
the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt
sources are named FIQ, SYS, and PID2 to PID31.
26.7 Functional Description
26.7.1 Interrupt Source Control
26.7.1.1 Interrupt Source Mode
The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR
(Source Mode Register) selects the interrupt condition of each source.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive
mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user.
The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered
or negative edge-triggered modes.
26.7.1.2 Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt
Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in
one instruction. The interrupt mask can be read in the AIC_IMR. A disabled interrupt does not affect servicing of other interrupts.
26.7.1.3 Interrupt Clearing and Setting
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respec-
tively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry activated when the
source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can
also be used to execute an AIC-implementation of a software interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source
being detected by the AIC as the current interrupt is affected by this operation. (Section 26.7.3.1 Priority Controller) The automatic clear
reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear
is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details,
see Section 26.7.4.5 Fast Forcing)
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
26.7.1.4 Interrupt Status
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Regis-
ter). AIC_IPR enables the actual activity of the sources, whether masked or not.
The AIC_ISR reads the number of the current interrupt (see Section 26.7.3.1 Priority Controller) and the register AIC_CISR gives an image
of the signals nIRQ and nFIQ driven on the processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.