Datasheet

SAM9G20
DS60001516A-page 286  2017 Microchip Technology Inc.
25.9.10 PMC Clock Generator PLL B Register
Name:CKGR_PLLBR
Access:Read/Write
Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
DIVB: Divider B
PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
OUTB: PLL B Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in Section 40.5.7 “PLL Characteristics”.
MULB: PLL B Multiplier
0: The PLL B is deactivated.
1–62: The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
USBDIV: Divider for USB Clock.
31 30 29 28 27 26 25 24
–– USBDIV ––––
23 22 21 20 19 18 17 16
–– MULB
15 14 13 12 11 10 9 8
OUTB PLLBCOUNT
76543210
DIVB
DIVB Divider Selected
0 Divider output is 0
1 Divider is bypassed
2–255 Divider output is the selected clock divided by DIVB.
USBDIV Divider Selected
0 0 Divider output is PLL B clock output
0 1 Divider output is PLL B clock output divided by 2
1 0 Divider output is PLL B clock output divided by 4
11Reserved