Datasheet

SAM9G20
DS60001516A-page 28  2017 Microchip Technology Inc.
8.2 Reset Controller
• Based on two Power-on-Reset cells
- one on VDDBU and one on VDDCORE
• Status of the last reset
- Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset
• Controls the internal resets and the NRST pin output
- Allows shaping a reset signal for the external devices
8.3 Shutdown Controller
• Shutdown and Wake-Up logic
- Software programmable assertion of the SHDN pin
- Deassertion Programmable on a WKUP pin level change or on alarm
8.4 Clock Generator
• Embeds a Low power 32768 Hz Slow Clock Oscillator and a Low power RC oscillator selectable with OSCSEL signal
- Provides the permanent Slow Clock SLCK to the system
• Embeds the Main Oscillator
- Oscillator bypass feature
- Supports 3 to 20 MHz crystals
• Embeds two PLLs
- The PLL A outputs 400–800 MHz clock
- The PLL B outputs 100 MHz clock
- Both integrate an input divider to increase output accuracy
- PLL A and PLL B embed their own filters
Figure 8-2: Clock Generator Block Diagram
On Chip
RC OSC
Power
Management
Controller
XIN
XOUT
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
ControlStatus
PLL and
Divider B
PLLB Clock
PLLBCK
XIN32
XOUT32
Slow Clock
Oscillator
Main
Oscillator
PLL and
Divider A
Clock Generator
OSCSEL