Datasheet

SAM9G20
DS60001516A-page 272  2017 Microchip Technology Inc.
25.8 Clock Switching Details
25.8.1 Master Clock Switching Timings
Table 25-1and Table 25-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This
is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected
clock has to be added.
Note 1: PLL designates either the PLL A or the PLL B Clock.
2: PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 25-1: Clock Switching Timings (Worst Case)
From Main Clock SLCK PLL Clock
To
Main Clock –
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 25-2: Clock Switching Timings (Worst Case)
From PLLA Clock PLLB Clock
To
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock
3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK