Datasheet

SAM9G20
DS60001516A-page 270  2017 Microchip Technology Inc.
Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR. This can be done
either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKB has been enabled
in the PMC_IER. All parameters in CKGR_PLLBR can be programmed in a single write operation. If at some stage one of the fol-
lowing parameters, MULB, DIVB is modified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked,
LOCKB will be set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s).
Code Example:
write_register(CKGR_PLLBR,0x20030602)
PLL B input clock is main clock divided by 2. PLL B output clock is PLL B input clock multiplied by 4. Once CKGR_PLLBR has been
written, LOCKB bit will be set after six slow clock cycles.
5. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR.
The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock
source is slow clock.
The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between different values (1, 2, 4, 8,
16, 32, 64). Prescaler output is the selected clock source divided by PRES parameter. By default, PRES parameter is set to 1 which
means that the input clock of the Master Clock and Processor Clock dividers is equal to slow clock.
The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1, 2, 3). The Master
Clock output is Master/Processor Clock Prescaler output divided by 1, 2, 4 or 6, depending on the value programmed in MDIV.
The PDIV field is used to control the Processor Clock divider. It is possible to choose between different values (0, 1). The Processor
Clock output is Master/Processor Clock Prescaler output divided by 1 or 2, depending on the value programmed in PDIV.
By default, MDIV and PDIV are set to 0, which indicates that Processor Clock is equal to the Master Clock.
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. This can be done either
by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled
in the PMC_IER.
The PMC_MCKR must not be programmed in a single write operation. The preferred programming sequence for the PMC_MCKR
is as follows:
• If a new value for CSS field corresponds to PLL Clock,
- Program the PRES field in the PMC_MCKR.
- Wait for the MCKRDY bit to be set in the PMC_SR.
- Program the CSS field in the PMC_MCKR.
- Wait for the MCKRDY bit to be set in the PMC_SR.
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
- Program the CSS field in the PMC_MCKR.
- Wait for the MCKRDY bit to be set in the PMC_SR.
- Program the PRES field in the PMC_MCKR.
- Wait for the MCKRDY bit to be set in the PMC_SR.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master
Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and
Processor Clocks.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR (CKGR_PLLAR
or CKGR_PLLBR), the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK (LOCKA or LOCKB)
goes high and MCKRDY is set. While PLLA is unlocked, the Master Clock selection is automatically changed to Slow Clock.
While PLLB is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see Sec-
tion 25.8.2 “Clock Switching Waveforms”.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)