Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 27
SAM9G20
8.1 System Controller Block Diagram
Figure 8-1: SAM9G20 System Controller Block Diagram
NRST
SLCK
Advanced
Interrupt
Controller
Real-time
Timer
Periodic Interval
Timer
Reset
Controller
PA0–PA31
periph_nreset
System Controller
Watchdog
Timer
wdt_fault
WDRPROC
PIO
Controllers
Power
Management
Controller
XIN
XOUT
MAINCK
PLLACK
pit_irq
MCK
proc_nreset
wdt_irq
periph_irq[2..4]
periph_nreset
periph_clk[2..27]
PCK
MCK
pmc_irq
nirq
nfiq
rtt_irq
Embedded
Peripherals
periph_clk[2..4]
pck[0–1]
in
out
enable
Arm926EJ-S
SLCK
SLCK
irq0–irq2
fiq
irq0–irq2
fiq
periph_irq[6..24]
periph_irq[2..24]
int
int
periph_nreset
periph_clk[6..24]
jtag_nreset
por_ntrst
proc_nreset
periph_nreset
dbgu_txd
dbgu_rxd
pit_irq
dbgu_irq
pmc_irq
rstc_irq
wdt_irq
rstc_irq
SLCK
Boundary Scan
TAP Controller
jtag_nreset
debug
PCK
debug
idle
debug
Bus Matrix
MCK
periph_nreset
proc_nreset
backup_nreset
periph_nreset
idle
Debug
Unit
dbgu_irq
MCK
dbgu_rxd
periph_nreset
dbgu_txd
rtt_alarm
Shutdown
Controller
SLCK
rtt0_alarm
backup_nreset
SHDN
WKUP
Four 32-bit
General-Purpose
Backup Registers
backup_nreset
XIN32
XOUT32
PLLBCK
PB0–PB31
PC0–PC31
VDDBU Powered
VDDCORE Powered
ntrst
VDDCORE
POR
Main
Oscillator
PLLA
VDDBU
POR
Slow Clock
Oscillator
PLLB
por_ntrst
VDDBU
rtt_irq
UDPCK
USB Device
Port
UDPCK
periph_nreset
periph_clk[10]
periph_irq[10]
USB Host
Port
periph_nreset
periph_clk[20]
periph_irq[20]
UHPCK
UHPCK
RC
Oscillator
OSCSEL