Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 269
SAM9G20
25.7 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR. In some cases it may be advantageous to define
a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR.
Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR to be set. This can be done
either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been
enabled in the PMC_IER.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished
via the CKGR_MCFR.
Once the MAINRDY field is set in CKGR_MCFR, the user may read the MAINF field in CKGR_MCFR. This provides the number
of main clock cycles within sixteen slow clock cycles.
3. Setting PLL A and divider A:
All parameters necessary to configure PLL A and divider A are located in the CKGR_PLLAR.
It is important to note that Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
The DIVA field is used to control the divider A itself. The user can program a value between 0 and 255. Divider A output is divider
A input divided by DIVA. By default, DIVA parameter is set to 0 which means that divider A is turned off.
The OUTA field is used to select the PLL A output frequency range.
The MULA field is the PLL A multiplier factor. This parameter can be programmed between 0 and 254. If MULA is set to 0, PLL A
will be turned off. Otherwise PLL A output frequency is PLL A input frequency multiplied by (MULA + 1).
The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR after CKGR_PLLAR has
been written.
Once CKGR_PLLAR has been written, the user is obliged to wait for the LOCKA bit to be set in the PMC_SR. This can be done
either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled
in the PMC_IER.
All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters,
MULA, DIVA is modified, LOCKA bit will go low to indicate that PLL A is not ready yet. When PLL A is locked, LOCKA will be set
again. User has to wait for LOCKA bit to be set before using the PLL A output clock.
Code Example:
write_register(CKGR_PLLAR,0x20030602)
PLL A input clock is main clock divided by 2. PLL An output clock is PLL A input clock multiplied by 4. Once CKGR_PLLAR has
been written, LOCKA bit will be set after six slow clock cycles.
4. Setting PLL B and divider B:
All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR.
The DIVB field is used to control divider B itself. A value between 0 and 255 can be programmed. Divider B output is divider B input
divided by DIVB parameter. By default DIVB parameter is set to 0 which means that divider B is turned off.
The OUTB field is used to select the PLL B output frequency range.
The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 62. If MULB is set to 0, PLL B
will be turned off, otherwise the PLL B output frequency is PLL B input frequency multiplied by (MULB + 1).
The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR after CKGR_PLLBR has
been written.