Datasheet

SAM9G20
DS60001516A-page 268 2017 Microchip Technology Inc.
Note: The Arm Wait for Interrupt mode is entered by a CP15 coprocessor operation. Refer to the Microchip application note, Opti-
mizing Power Consumption of AT91SAM9261-based Systems, lit. number 6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data trans-
fers from other masters of the system bus.
25.4 USB Clock Controller
The USB Source Clock is always generated from the PLL B output. If using the USB, the user must program the PLL to generate a 48
MHz or a 96 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see Figure 25-2).
When the PLL B output is stable, i.e., the LOCKB is set:
The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the
user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host port require both
the 12/48 MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock Controller.
Figure 25-2: USB Clock Controller
25.5 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The
user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER)
and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status
Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed oper-
ation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier
defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.
25.6 Programmable Clock Output Controller
The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx reg-
isters.
PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B output and the main clock by writing the CSS
field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in
PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively.
Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the
Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to dis-
able the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/4
UHP Clock (UHPCK)
UHP