Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 267
SAM9G20
25. Power Management Controller (PMC)
25.1 Overview
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC
enables/disables the clock inputs to many of the peripherals and the Arm Processor.
The Power Management Controller provides the following clocks:
• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to
the modules running permanently, such as the AIC and the Memory Controller.
• Processor Clock (PCK), switched off when entering processor in idle mode.
• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently
controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in this datasheet.
• UHP Clock (UHPCK), required by USB Host Port operations.
• Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins.
25.2 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals
and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock
signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which allows the pro-
cessor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The pres-
caler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler.
The Master Clock divider can be programmed through the MDIV field in PMC_MCKR.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock
is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a
high-speed clock to a lower one to inform the software when the change is actually done.
Figure 25-1: Master Clock Controller
25.3 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled
by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the Sys-
tem Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is
achieved by disabling the Processor Clock and entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
SLCK
Master Clock
Prescaler
MCK
PRESCSS
Master
Clock
Divider
MAINCK
PLLACK
PLLBCK
MDIV
To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR
PMC_MCKR
Processor
Clock
Divider
PMC_MCKR
PDIV