Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 253
SAM9G20
23.4 Peripheral DMA Controller (PDC) User Interface
Note 1: PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.)
Table 23-1: Register Mapping
Offset Register Name
(1)
Access Reset
0x100 Receive Pointer Register PERIPH_RPR Read/Write 0
0x104 Receive Counter Register PERIPH_RCR Read/Write 0
0x108 Transmit Pointer Register PERIPH_TPR Read/Write 0
0x10C Transmit Counter Register PERIPH_TCR Read/Write 0
0x110 Receive Next Pointer Register PERIPH_RNPR Read/Write 0
0x114 Receive Next Counter Register PERIPH_RNCR Read/Write 0
0x118 Transmit Next Pointer Register PERIPH_TNPR Read/Write 0
0x11C Transmit Next Counter Register PERIPH_TNCR Read/Write 0
0x120 Transfer Control Register PERIPH_PTCR Write-only –
0x124 Transfer Status Register PERIPH_PTSR Read-only 0