Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 251
SAM9G20
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel
is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/
RXTDIS in the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the peripheral status
register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 23.3.3 Transfer Counters and to the associated peripheral user inter-
face.
23.3.2 Memory Pointers
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have 32-bit memory
pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory pointers, one for
current transfer and the other for next transfer. These pointers point to transmit or receive data depending on the operating mode of the
peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new address.
23.3.3 Transfer Counters
Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define the size of data
to be transferred by the channel. The current transfer counter is decremented first as the data addressed by current memory pointer starts
to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer counter. If the value of next counter
is zero, the channel stops transferring data and sets the appropriate flag. But if the next counter value is greater then zero, the values of
the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next
pointer/next counter get zero/zero as values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status
Register.
The following list gives an overview of how status register flags behave depending on the counters’ values:
• ENDRX flag is set when the PERIPH_RCR reaches zero.
• RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
• ENDTX flag is set when the PERIPH_TCR reaches zero.
• TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the Peripheral Status Register.
23.3.4 Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in
the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access
to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding Register (RHR). The read
data are stored in an internal buffer and then written to memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests access to the Matrix.
When access is granted, the PDC transmit channel reads data from memory and puts them to Transmit Holding Register (THR) of its
associated peripheral. The same peripheral sends data according to its mechanism.
23.3.5 PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral.
All these flags are only visible in the Peripheral Status Register.
Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels.
23.3.5.1 Receive Transfer End
This flag is set when PERIPH_RCR reaches zero and the last data has been transferred to memory.
It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.
23.3.5.2 Transmit Transfer End
This flag is set when PERIPH_TCR reaches zero and the last data has been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.