Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 25
SAM9G20
• Multiple Wait State Management
- Programmable Wait State Generation
- External Wait Request
- Programmable Data Float Time
• Slow Clock mode supported
7.2.3 SDRAM Controller
• Supported devices
- Standard and Low-power SDRAM (Mobile SDRAM)
• Numerous configurations supported
- 2K, 4K, 8K Row Address Memory Parts
- SDRAM with two or four Internal Banks
- SDRAM with 16- or 32-bit Datapath
• Programming facilities
- Word, half-word, byte access
- Automatic page break when Memory Boundary has been reached
- Multibank Ping-pong Access
- Timing parameters specified by software
- Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
- Self-refresh, power down and deep power down modes supported
• Error detection
- Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
7.2.4 Error Correction Code Controller
• Hardware Error Correction Code (ECC) Generation
- Detection and Correction by Software
• Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path.
• Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software
• Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data Path
• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path
• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path