Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 249
SAM9G20
23. Peripheral DMA Controller (PDC)
23.1 Overview
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link
between the PDC and a serial peripheral is operated by the AHB to ABP bridge.
The PDC contains 24 channels. The full-duplex peripherals feature 21 mono directional channels used in pairs (transmit only or receive
only). The half-duplex peripherals feature 1 bi-directional channel.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface of mono direc-
tional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for
current transfer and one set (pointer, counter) for next transfer. The bi-directional channel user interface contains four 32-bit memory point-
ers and four 16-bit counters. Each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock
cycles required for a data transfer, which improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed
data is transferred, an end of transfer interrupt is generated by the peripheral itself.