Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 23
SAM9G20
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB)
for its Master and Slave interfaces with additional features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 7 are directed to the EBI that associates
these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a
second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the
Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the
mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 (Arm926 Instruction and Data), three different Slaves are assigned to the memory space decoded at
address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 7-1 ”Internal Memory Mapping” for details.
7.1 Embedded Memories
• 64 Kbyte ROM
- Single Cycle Access at full matrix speed
• Two 16 Kbyte Fast SRAM
- Single Cycle Access at full matrix speed
7.1.1 Boot Strategies
Table 7-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset.
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured
with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has
booted. When REMAP = 1, BMS is ignored. Refer to Section 18. “SAM9G20 Bus Matrix” for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware
at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete
memory map presented in Figure 7-1.
The SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped
between address 0x0 and 0x000F FFFF is reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
7.1.1.1 BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• Boot on slow clock (On-chip RC or 32768 Hz)
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
Table 7-1: Internal Memory Mapping
Address
REMAP = 0
REMAP = 1BMS = 1 BMS = 0
0x0000 0000 ROM EBI_NCS0 SRAM0 16 KB
0x0010 0000 ROM
0x0020 0000 SRAM0 16 KB
0x0030 0000 SRAM1 16 KB
0x0050 0000 USB Host User Interface