Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 21
SAM9G20
6.3 Peripheral DMA Controller
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-four channels
- Two for each USART
- Two for the Debug Unit
- Two for the Serial Synchronous Controller
- Two for each Serial Peripheral Interface
- One for Multimedia Card Interface
- One for Analog-to-Digital Converter
- Two for the Two-wire Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
- TWI Transmit Channel
- DBGU Transmit Channel
- USART5 Transmit Channel
- USART4 Transmit Channel
- USART3 Transmit Channel
- USART2 Transmit Channel
- USART1 Transmit Channel
- USART0 Transmit Channel
- SPI1 Transmit Channel
- SPI0 Transmit Channel
- SSC Transmit Channel
- TWI Receive Channel
- DBGU Receive Channel
- USART5 Receive Channel
- USART4 Receive Channel
- USART3 Receive Channel
- USART2 Receive Channel
- USART1 Receive Channel
- USART0 Receive Channel
- ADC Receive Channel
- SPI1 Receive Channel
- SPI0 Receive Channel
- SSC Receive Channel
- MCI Transmit/Receive Channel
6.4 Debug and Test Features
• Arm926 Real-time In-circuit Emulator
- Two real-time Watchpoint Units
- Two Independent Registers: Debug Control Register and Debug Status Register
- Test Access Port Accessible through JTAG Protocol
- Debug Communications Channel
• Debug Unit
- Two-pin UART
- Debug Communication Channel Interrupt Handling
- Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins