Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 209
SAM9G20
22. Error Correction Code Controller (ECC)
22.1 Overview
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia
lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code.
The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors
in data. The ECC controller is capable of single bit error correction and 2-bit random detection. When NAND Flash/SmartMedia have more
than 2 bits of errors, the data cannot be corrected.
The ECC user interface is compliant with the Arm Advanced Peripheral Bus (APB rev2).
22.2 Block Diagram
Figure 22-1: Block Diagram
22.3 Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The
page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words
in the extra area used for redundancy.
Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the
NAND Flash device, NAND Flash providers recommend to utilize either 1 ECC per 256 bytes of data, 1 ECC per 512 bytes of data or 1
ECC for all of the page.
The only configurations required for ECC are the NAND Flash or the SmartMedia page size (528/2112/4224) and the type of correction
wanted (1 ECC for all the page/1 ECC per 256 bytes of data /1 ECC per 512 bytes of data). Page size is configured setting the PAGESIZE
field in the ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPCORRECT field in the ECC Mode Register
(ECC_MR).
User Interface
Ctrl/ECC Algorithm
Static
Memory
Controller
APB
NAND Flash
SmartMedia
Logic
ECC
Controller