Datasheet

SAM9G20
DS60001516A-page 20  2017 Microchip Technology Inc.
6.2.1 Matrix Masters
The Bus Matrix of the SAM9G20 manages six Masters, which means that each master can perform an access concurrently with others,
according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have
the same decodings.
6.2.2 Matrix Slaves
Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave.
6.2.3 Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, like as example allowing access from the
Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown “–” in Table 6-3.
Table 6-1: List of Bus Matrix Masters
Master 0 Arm926
™
Instruction
Master 1 Arm926 Data
Master 2 PDC
Master 3 ISI Controller
Master 4 Ethernet MAC
Master 5 USB Host DMA
Table 6-2: List of Bus Matrix Slaves
Slave 0 Internal SRAM0 16 Kbytes
Slave 1 Internal SRAM1 16 Kbytes
Slave 2
Internal ROM
USB Host User Interface
Slave 3 External Bus Interface
Slave 4 Internal Peripherals
Table 6-3: SAM9G20 Masters to Slaves Access
Master 0 & 1 2 3 4 5
Slave
Arm926
Instruction &
Data
Peripheral DMA
Controller
ISI Controller Ethernet MAC
USB Host
Controller
0 Internal SRAM 16 Kbytes X X X X X
1 Internal SRAM 16 Kbytes X X X X X
2
Internal ROM X X – – –
UHP User Interface X X – – –
3 External Bus Interface X X X X X
4 Internal Peripherals X X – – –