Datasheet

SAM9G20
DS60001516A-page 196  2017 Microchip Technology Inc.
Figure 21-7: Low-power Mode Behavior
21.5.5.3 Deep Power-down Mode
This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal
voltage generators inside the SDRAM are stopped and all data is lost.
When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (See Section 21.4.1
SDRAM Device Initialization).
This is described in the following figure.
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
(input)
T
RCD
= 3
Dna Dnb Dnc Dnd
Dne
Dnf
Row n col a col b col c col d col e col f
CAS = 2
SDCKE
Low Power Mode