Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 195
SAM9G20
Figure 21-6: Self-refresh Mode Behavior
21.5.5.2 Low-power Mode
This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in
self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast
to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device
refresh operation). As no auto-refresh operations are performed by the SDRAM itself, the SDRAM Controller carries out the refresh oper-
ation. The exit procedure is faster than in self-refresh mode.
This is described in Figure 21-7.
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
Self Refresh Mode
SDWE
Row
T
XSR
= 3
SDCKE
Write
SDRAMC_SRR
SRCB = 1
Access Request
to the SDRAM Controller