Datasheet

SAM9G20
DS60001516A-page 194  2017 Microchip Technology Inc.
21.5.4 SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and
incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An inter-
nal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform. It is acknowledged by reading the Interrupt
Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU
tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. See Figure 21-5.
Figure 21-5: Refresh Cycle Followed by a Read Access
21.5.5 Power Management
Three low-power modes are available:
• Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM Controller. Current drained by the
SDRAM is very low.
• Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh cycles, the SDRAM is in
power-down. Current drained in Power-down mode is higher than in Self-refresh Mode.
• Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are lost, but the SDRAM does not drain any
current.
The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in
self-refresh and power-down mode after the last access by programming a timeout value in the Low Power Register.
21.5.5.1 Self-refresh Mode
This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh mode, the SDRAM device
retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to
the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Con-
troller provides a sequence of commands and exits self-refresh mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the SDRAM array. This
feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self
Refresh (PASR) and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM
during initialization.
The SDRAM device must remain in self-refresh mode for a minimum period of t
RAS
and may remain in self-refresh mode for an indefinite
period. This is described in Figure 21-6.
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
(input)
t
RP
= 3
SDWE
Dnb
Dnc
Dnd
col c col d
CAS = 2
Row m
col a
t
RC
= 8 t
RCD
= 3
Dma
Row n