Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 193
SAM9G20
Figure 21-3: Read Burst, 32-bit SDRAM Access
21.5.3 Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates
a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an addi-
tional clock cycle is inserted between the precharge/active (t
RP
) command and the active/read (t
RCD
) command. This is described in
Figure 21-4 below.
Figure 21-4: Read Burst with Boundary Row Access
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
(Input)
t
RCD
= 3
Dna
SDWE
Dnb Dnc Dnd
Dne
Dnf
Row n col a col b col c col d col e col f
CAS = 2
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
T
RP
= 3
SDWE
Row m
col a
col a col b col c col d col e
Dna Dnb
Dnc
Dnd
T
RCD
= 3 CAS = 2
col b
col c
col d
Dma Dmb
Dmc
Dmd
Row n
Dme