Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 191
SAM9G20
Figure 21-1: SDRAM Device Initialization Sequence
21.4.2 I/O Lines
The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO
controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the SDRAM Controller are not used by the appli-
cation, they can be used for other purposes by the PIO Controller.
21.4.3 Interrupt
The SDRAM Controller interrupt (Refresh Error notification) is connected to the Memory Controller. This interrupt may be ORed with other
System Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Con-
troller).
Using the SDRAM Controller interrupt requires the AIC to be programmed first.
21.5 Functional Description
21.5.1 SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each
bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master
requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a
write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller
generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, addi-
tional clock cycles are inserted between precharge/active (t
RP
) commands and active/write (t
RCD
) commands. For definition of these timing
parameters, refer to the “SDRAMC Configuration Register” . This is described in Figure 21-2 below.
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
NBS
Inputs Stable for
200 μsec
Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command
SDCKE
t
RP
t
RC
t
MRD