Datasheet
2017 Microchip Technology Inc. DS60001516A-page 19
SAM9G20
6. Processor and Architecture
6.1 Arm926EJ-S Processor
• RISC Processor Based on Arm v5TEJ Architecture with Jazelle technology for Java acceleration
• Two Instruction Sets
- Arm High-performance 32-bit Instruction Set
- Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
- Instruction Fetch (F)
- Instruction
Decode (D)
- Execute (E)
- Data Memory (M)
- Register Write (W)
• 32-Kbyte Data Cache, 32-Kbyte Instruction Cache
- Virtually-addressed 4-way Associative Cache
- Eight words per line
- Write-through and Write-back Operation
- Pseudo-random or Round-robin Replacement
• Write Buffer
- Main Write Buffer with 16-word Data Buffer and 4-address Buffer
- DCache Write-back Buffer with 8-word Entries and a Single Address Entry
- Software Control Drain
• Standard Arm v4 and v5 Memory Management Unit (MMU)
- Access Permission for Sections
- Access Permission for large pages and small pages can be specified separately for each quarter of the page
- 16 embedded domains
• Bus Interface Unit (BIU)
- Arbitrates and Schedules AHB Requests
- Separate Masters for both instruction and data access providing complete Matrix system flexibility
- Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
- On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
6.2 Bus Matrix
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
- Fixed-priority Arbitration
- Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
• Burst Management
- Breaking with Slot Cycle Limit Support
- Undefined Burst Length Support
• One Address Decoder provided per Master
- Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after
remap
• Boot Mode Select
- Non-volatile Boot Memory can be internal or external
- Selection is made by BMS pin sampled at reset
• Remap Command
- Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
• Allows Handling of Dynamic Exception Vectors