Datasheet
2017 Microchip Technology Inc. DS60001516A-page 189
SAM9G20
21.3.1.2 16-bit Memory Data Bus Width
Note 1: M0 is the byte address inside a 16-bit half-word.
2: Bk[1] = BA1, Bk[0] = BA0.
Table 21-5: SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[10:0] Column[7:0]
M0
Bk[1:0] Row[10:0] Column[8:0]
M0
Bk[1:0] Row[10:0] Column[9:0]
M0
Bk[1:0] Row[10:0] Column[10:0]
M0
Table 21-6: SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[11:0] Column[7:0]
M0
Bk[1:0] Row[11:0] Column[8:0]
M0
Bk[1:0] Row[11:0] Column[9:0]
M0
Bk[1:0] Row[11:0] Column[10:0]
M0
Table 21-7: SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[12:0] Column[7:0]
M0
Bk[1:0] Row[12:0] Column[8:0]
M0
Bk[1:0] Row[12:0] Column[9:0]
M0
Bk[1:0] Row[12:0] Column[10:0]
M0