Datasheet

SAM9G20
DS60001516A-page 176  2017 Microchip Technology Inc.
20.12 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Man-
agement Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the
user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid repro-
gramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip
selects.
20.12.1 Slow Clock Mode Waveforms
Figure 20-31 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 20-5 indicates the value
of read and write parameters in slow clock mode.
Figure 20-31: Read/Write Cycles in Slow Clock Mode
20.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the
set of slow clock mode parameters. See Figure 20-32. The external device may not be fast enough to support such timings.
Figure 20-33 illustrates the recommended procedure to properly switch from one mode to the other.
Table 20-5: Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRD_SETUP 1 NWE_SETUP 1
NRD_PULSE 1 NWE_PULSE 1
NCS_RD_SETUP 0 NCS_WR_SETUP 0
NCS_RD_PULSE 2 NCS_WR_PULSE 3
NRD_CYCLE 2 NWE_CYCLE 3
A[ 25:2]
NCS
1
MCK
NWE 1
1
NWE_CYCLE = 3
A [25:2]
MCK
NRD
NRD_CYCLE = 2
1
1
NCS
SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS0, NBS1,
NBS2, NBS3,
A0,A1