Datasheet

SAM9G20
DS60001516A-page 170  2017 Microchip Technology Inc.
Figure 20-25: TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
20.11 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE
register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set
to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write oper-
ation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select.
20.11.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that
reason, the NWAIT signal cannot be used in Page Mode (“Asynchronous Page Mode”), or in Slow Clock Mode (“Slow Clock Mode”).
The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by
the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has
no impact on SMC behavior.
20.11.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen,
i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted,
the SMC completes the access, resuming the access from the point where it was stopped. See Figure 20-26. This mode must be selected
when the external device uses the NWAIT signal to delay the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 20-27.
TDF_CYCLES = 5
TDF_CYCLES = 5
TDF_MODE = 0
(optimization disabled)
A
[25:2]
read1 cycle
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[31:0]
read1 hold = 1
write2 cycle
write2 setup = 1
4 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1