Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 169
SAM9G20
Figure 20-23: TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on
different chip selects
Figure 20-24: TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
TDF_CYCLES = 6
TDF_CYCLES = 6
TDF_MODE = 0
(optimization disabled)
A[
25:2]
read1 cycle
Chip Select Wait State
MCK
read1 controlling signal
(NRD)
read2 controlling signal
(NRD)
D[31:0]
read1 hold = 1
read 2 cycle
read2 setup = 1
5 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1
TDF_CYCLES = 4
TDF_CYCLES = 4
TDF_MODE = 0
(optimization disabled)
A
[25:2]
read1 cycle
Chip Select
Wait State
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[31:0]
read1 hold = 1
write2 cycle
write2 setup = 1
2 TDF WAIT STATES
NBS0, NBS1,
NBS2, NBS3,
A0, A1