Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 165
SAM9G20
Figure 20-19: Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read, 1 Set-up Cycle
20.9.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next
access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next
accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming
the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State
is inserted, even if the change does not concern the current Chip Select.
20.9.3.1 User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If the user
only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modifica-
tion by writing the SMC_MODE, even if no change was made on the mode parameters.
20.9.3.2 Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer
(see Section 20.12 “Slow Clock Mode”).
20.9.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 20-16.
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
write cycle
(WRITE_MODE = 1)
Early Read
wait state
MCK
NRD
internal write controlling signal
external write controlling signal
(NWE)
D[31:0]
read cycle
(READ_MODE = 0 or READ_MODE = 1)
no hold
read setup = 1