Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 163
SAM9G20
Figure 20-16: Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
20.9.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before
the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only
occurs between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 20-17).
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter
is set to 0, regardless of the read mode (Figure 20-18). The write operation must end with a NCS rising edge. Without an Early Read
Wait State, the write operation could not complete properly.
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control sig-
nal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected
due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle.
See Figure 20-19.
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS0
NRD_CYCLE
Chip Select
Wait State
NWE_CYCLE
MCK
NCS2
NRD
NWE
D[31:0]
Read to Write
Wait State