Datasheet

SAM9G20
DS60001516A-page 160  2017 Microchip Technology Inc.
20.8.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write
cycles in the same memory (see Figure 20-13). However, for devices that perform write operations on the rising edge of NWE or NCS,
such as SRAM, either a setup or a hold must be programmed.
Figure 20-13: Null Setup and Hold Values of NCS and NWE in Write Cycle
20.8.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
20.8.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write oper-
ation.
20.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):
Figure 20-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold
steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regard-
less of the programmed waveform on NCS.
NCS
MCK
NWE,
NWR0, NWR1,
NWR2, NWR3
D[31:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1