Datasheet

SAM9G20
DS60001516A-page 16  2017 Microchip Technology Inc.
Figure 4-1: VDDCORE and VDDIO Constraints at Startup
VDDCORE and VDDBU are controlled by Power-on-Reset (POR) to guarantee that these power sources reach their target values prior
to the release of POR. (See Figure 4-1.)
• VDDIOM and VDDIOP must NOT be powered until VDDCORE has reached a level superior or equal to V
T+
(0.5V).
• VDDIOP must be ≥ V
IH
(refer to Table 40-2 ”DC Characteristics” for more details), (t
RST
+ t
1
) at the latest, after VDDCORE has
reached V
T+
.
• VDDIOM must reach V
OH
(refer to Table 40-2 ”DC Characteristics” for more details), (t
RST
+ t
1
+ t
2
) at the latest, after VDDCORE
has reached V
T+
.
•t
2
= t
RST
= 30 µs
•t
3
= 3 × t
SLCK
•t
4
= 14 × t
SLCK
The t
SLCK
min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz). This gives:
•t
2
= t
RST
= 30 µs
•t
3
= 66 µs
•t
4
= 308 µs
Figure 4-2 shows an example of the implementation on the evaluation kit AT91SAM9G20-EK Rev.C.
VDD (V)
Core Supply POR output
VDDIOtyp
V
T+
(0.5V)
SLCK
VDDCOREtyp
0.7V
VDDCORE
VDDIO
VDDIO >
V
OH
V
OH
(2.6V)
t
<--------------------- t
1
----------------------> < t
3
>
< t
2
>
<------------- t
4
------------>