Datasheet

SAM9G20
DS60001516A-page 158  2017 Microchip Technology Inc.
Figure 20-10: READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
20.8.2.2 Read is Controlled by NCS (READ_MODE = 0)
Figure 20-11 shows the typical read cycle of an LCD module. The read data is valid t
PACC
after the falling edge of the NCS signal and
remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0
(read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS,
whatever the programmed waveform of NRD may be.
Figure 20-11: READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
Data Sampling
t
PACC
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD
D[31:0]
Data Sampling
t
PACC
MCK
D[31:0]
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD