Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 157
SAM9G20
All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the
NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the
NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
20.8.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive
read cycles in the same memory (see Figure 20-9).
Figure 20-9: No Setup, No Hold On NRD and NCS Read Signals
20.8.1.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
20.8.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data
bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE
register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation.
20.8.2.1 Read is Controlled by NRD (READ_MODE = 1):
Figure 20-10 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available t
PACC
after the falling
edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD),
to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock
that generates the rising edge of NRD, whatever the programmed waveform of NCS may be.
MCK
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE NRD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_CYCLE NRD_CYCLE
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD
D[31:0]