Datasheet

SAM9G20
DS60001516A-page 156  2017 Microchip Technology Inc.
20.8.1 Read Waveforms
The read cycle is shown on Figure 20-8.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
Figure 20-8: Standard Read Cycle
20.8.1.1 NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.
20.8.1.2 NCS Waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
20.8.1.3 Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the
point where address may change. The total read cycle time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD_SETUP NRD_PULSE NRD_HOLD
MCK
NRD
D[31:0]
NCS_RD_SETUP
NCS_RD_PULSE
NCS_RD_HOLD
NRD_CYCLE