Datasheet

SAM9G20
DS60001516A-page 150  2017 Microchip Technology Inc.
20. Static Memory Controller (SMC)
20.1 Overview
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices.
It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices.
Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully
parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow
clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals.
The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes.
20.2 I/O Lines Description
20.3 Multiplexed Signals
Table 20-1: I/O Line Description
Name Description Type Active Level
NCS[7:0] Static Memory Controller Chip Select Lines Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low
NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low
A1/NWR2/NBS2 Address Bit 1/Write 2/Byte 2 Select Signal Output Low
NWR3/NBS3 Write 3/Byte 3 Select Signal Output Low
A[25:2] Address Bus Output
D[31:0] Data Bus I/O
NWAIT External Wait Signal Input Low
Table 20-2: Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals Related Function
NWR0 NWE Byte-write or byte-select access, see “Byte Write or Byte Select Access”.
A0 NBS0 8-bit or 16-/32-bit data bus, see “Data Bus Width”.
NWR1 NBS1 Byte-write or byte-select access see “Byte Write or Byte Select Access”.
A1 NWR2 NBS2
8-/16-bit or 32-bit data bus, see “Data Bus Width”.
Byte-write or byte-select access, see “Byte Write or Byte Select Access”.
NWR3 NBS3 Byte-write or byte-select access see “Byte Write or Byte Select Access”.