Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 15
SAM9G20
4. Power Considerations
4.1 Power Supplies
The SAM9G20 has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have sep-
arate grounds. See Table 4-1.
4.2 Programmable I/O Lines
The power supply pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V
external memories.
The maximum speed is 133 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF. The other signals (control, address and data signals)
do not go over 66 MHz, loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V.
The EBI I/Os accept two slew rate modes, Fast and Slow. This allows to adapt the rising and falling time on SDRAM clock, control and
data to the bus load.
The voltage ranges and the slew rates are determined by programming VDDIOMSEL and IOSR bits in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. The user must make sure
to program the EBI voltage range before getting the device out of its Slow Clock mode.
At reset, the selected slew rates defaults are Fast.
4.3 Power Sequence Requirements
The SAM9G20 board design must comply with the power-up and power-down sequence guidelines described in the following sections to
guarantee reliable operation of the device. Any deviation from these sequences may lead to the following situations:
• Excessive current consumption during the power-up phase which, in the worst case, can result in irreversible damage to the device.
• Prevent the device from booting.
4.3.1 Power-up Sequence
The power sequence described below is applicable to all the SAM9G20 revisions. However, the power sequence can be simplified for the
revision B device. In this revision, the over consumption during the power-up phase has been limited to less than 200 mA. This current
can not damage the device and if it is acceptable for the final application, the power sequence becomes VDDIO followed by VDDCORE.
VDDIO must be established first (> 0.7V) to ensure a correct sampling of the BMS signal and also to guarantee the correct voltage level
when accessing an external memory.
Table 4-1: SAM9G20 Power Supply Pins
Pin(s) Item(s) powered Range Nominal Ground
VDDCORE
Core, including the processor
Embedded memories
Peripherals
0.9–1.1 V 1.0V
GND
VDDIOM External Bus Interface I/O lines
1.65–1.95 V 1.8V
3.0–3.6 V 3.3V
VDDOSC Main Oscillator cells 1.65–3.6 V –
VDDIOP Peripherals I/O lines
1.65–1.95 V 1.8V
3.0–3.6 V 3.3V
VDDBU
Slow Clock oscillator
Internal RC oscillator
Part of the System Controller
0.9–1.1 V 1.0V GNDBU
VDDPLL PLL cells 0.9–1.1 V 1.0V GNDPLL
VDDUSB USB transceiver 3.0–3.6 V 3.3V GNDUSB
VDDANA Analog-to-Digital Converter 3.0–3.6 V 3.3V GNDANA