Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 141
SAM9G20
19.7 Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer website to check
current device availability.
19.7.1 16-bit SDRAM
Figure 19-8: Hardware Configuration - 16-bit SDRAM
19.7.1.1 Software Configuration - 16-bit SDRAM
The following configuration has to be performed:
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the
bus matrix memory space.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 16 bits.
The SDRAM initialization sequence is described in Section 21.4.1 “SDRAM Device Initialization”.
D13
D12
D8
D7
D3
D11
D2
D14
D4
D0
RAS
D1
D10
CAS
SDA10
SDCK
D9
SDWE
SDCKE
D5
D15
D6
A4
A9
A14
A5
A2
A6
A3
BA0
A10
A13
A8
BA1
A7
A11
A0
RAS
CAS
SDA10
SDWE
SDCKE
SDCK
CFIOR_NBS1_NWR1
SDCS_NCS1
BA0
BA1
D[0..15]
A[0..14]
3V3
1%6
256 Mbits
1%6
(Not used A12)
TSOP54 PACKAGE
C1 1C1 1
C7 1C7 1
C2 1C2 1
MT48LC16M16A2
U1
MT48LC16M16A2
U1
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10
22
BA0
20
A12
36
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
42
DQ9
44
DQ10
45
DQ11
47
DQ12
48
DQ13
50
DQ14
51
DQ15
53
VDD
1
VSS
28
VSS
41
VDDQ
3
VDD
27
N.C
40
CLK
38
CKE
37
DQML
15
DQMH
39
CAS
17
RAS
18
WE
16
CS
19
VDDQ
9
VDDQ
43
VDDQ
49
VSSQ
6
VSSQ
12
VSSQ
46
VSSQ
52
VDD
14
VSS
54
A11
35
BA1
21
C3 1C3 1
C4 1C4 1
C5 1C5 1
C6 1C6 1