Datasheet

SAM9G20
DS60001516A-page 140  2017 Microchip Technology Inc.
Figure 19-6: NAND Flash Signal Multiplexing on EBI Pins
19.6.7.2 NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the
EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address
within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines.
The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode.
Figure 19-7: NAND Flash Application Example
Note: The External Bus Interface is also able to support 16-bit devices.
SMC
NRD_NOE
NWR0_NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx
NANDWE
NANDOE
D[7:0]
ALE
NANDWE
NANDOE
NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO
R/B
EBI
CE
NAND Flash
PIO
NCSx/NANDCS
Not Connected