Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 137
SAM9G20
19.6.6.3 Read/Write Signals
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW
signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC
signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 19-4 illustrates a schematic
representation of this logic.
Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4
(and/or NCS5) chip select to the appropriate values.
Figure 19-4: CompactFlash Read/Write Control Signals
True IDE Mode
Task File 1 0 8 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Data Register 1 0 16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
Alternate True IDE Mode
Control Register
Alternate Status Read
0 1 Don’t Care Access to Even Byte on D[7:0] Don’t Care
Drive Address 0 1 8 bits Access to Odd Byte on D[7:0]
Standby Mode or Address Space
is not assigned to CF
11–– –
Table 19-7: CompactFlash Mode Selection
Mode Base Address CFOE CFWE CFIOR CFIOW
Attribute Memory
Common Memory
NRD NWR0_NWE 1 1
I/O Mode 1 1 NRD NWR0_NWE
True IDE Mode 0 1 NRD NWR0_NWE
Table 19-6: CFCE1 and CFCE2 Truth Table (Continued)
Mode CFCE2 CFCE1 DBW Comment SMC Access Mode
SMC
NRD_NOE
NWR0_NWE
A23
CFIOR
CFIOW
CFOE
CFWE
1
1
CompactFlash Logic
External Bus Interface
1
1
1
0
A22
1
0
1
0
1
0