Datasheet

SAM9G20
DS60001516A-page 136  2017 Microchip Technology Inc.
Figure 19-3: CompactFlash Memory Mapping
Note: The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode).
19.6.6.2 CFCE1 and CFCE2 Signals
To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the D[7:0]
bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS4 or NCS5). The DBW
field in the SMC MODE Register corresponding to the NCS4 and/or NCS5 address space must be configured as shown in Table 19-6 to
enable the required access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding
Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer
to Section 20. “Static Memory Controller (SMC)”.
Table 19-5: CompactFlash Mode Selection
A[23:21] Mode Base Address
000 Attribute Memory
010 Common Memory
100 I/O Mode
110 True IDE Mode
111 Alternate True IDE Mode
Table 19-6: CFCE1 and CFCE2 Truth Table
Mode CFCE2 CFCE1 DBW Comment SMC Access Mode
Attribute Memory NBS1 NBS0 16 bits Access to Even Byte on D[7:0] Byte Select
Common Memory
NBS1 NBS0 16bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
1 0 8 bits Access to Odd Byte on D[7:0]
I/O Mode
NBS1 NBS0 16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
1 0 8 bits Access to Odd Byte on D[7:0]
CF Address Space
Attribute Memory Mode Space
Common Memory Mode Space
I/O Mode Space
True IDE Mode Space
True IDE Alternate Mode Space
Offset 0x00E0 0000
Offset 0x00C0 0000
Offset 0x0080 0000
Offset 0x0040 0000
Offset 0x0000 0000