Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 135
SAM9G20
19.6.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals
through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while
no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers.
Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Controller without delaying the other external Mem-
ory Controller accesses.
19.6.2 Pull-up Control
The EBI Chip Select Assignment Register (EBI_CSA) in Section 18.6 “Chip Configuration User Interface” permits enabling of on-chip pull-
up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the
EBI_CSA.EBI_DBPUC bit disables the pull-up resistors on the lines D0–D15. Enabling the pull-up resistor on the lines D16–D31 can be
performed by programming the appropriate PIO controller.
19.6.3 Static Memory Controller
For information on the Static Memory Controller, refer to Section 20. “Static Memory Controller (SMC)”.
19.6.4 SDRAM Controller
For information on the SDRAM Controller, refer to Section 21. “SDRAM Controller (SDRAMC)”.
19.6.5 ECC Controller
For information on the ECC Controller, refer to Section 22. “Error Correction Code Controller (ECC)”.
19.6.6 CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address space. Programming the
EBI_CS4A and/or EBI_CS5A bit in the EBI_CSA register to the appropriate value enables this logic. For details on this register, refer to
Section 18. “SAM9G20 Bus Matrix”. Access to an external CompactFlash device is then made by accessing the address space reserved
to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True
IDE modes) and _ATA SEL (True IDE mode) are not handled.
19.6.6.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode
Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attri-
bute memory mode and True IDE mode.
The different modes are accessed through a specific memory mapping as illustrated on Figure 19-3. A[23:21] bits of the transfer address
are used to select the desired mode as described in Table 19-5.