Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 131
SAM9G20
Table 19-2 details the connections between the two memory controllers and the EBI pins.
19.4 Application Example
19.4.1 Hardware Interface
Table 19-3 details the connections to be applied between the EBI pins and the external devices for each memory controller.
Table 19-2: EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins SDRAMC I/O Lines SMC I/O Lines
EBI_NWR1/NBS1/CFIOR NBS1 NWR1/NUB
EBI_A0/NBS0 Not Supported SMC_A0/NLB
EBI_A1/NBS2/NWR2 Not Supported SMC_A1
EBI_A[11:2] SDRAMC_A[9:0] SMC_A[11:2]
EBI_SDA10 SDRAMC_A10 Not Supported
EBI_A12 Not Supported SMC_A12
EBI_A[14:13] SDRAMC_A[12:11] SMC_A[14:13]
EBI_A[22:15] Not Supported SMC_A[22:15]
EBI_A[25:23] Not Supported SMC_A[25:23]
EBI_D[31:0] D[31:0] D[31:0]
Table 19-3: EBI Pins and External Static Devices Connections
Signals: EBI_
Pins of the SMC Interfaced Device
8-bit
Static Device
2 x 8-bit
Static Devices
16-bit
Static Device
4 x 8-bit
Static Devices
2 x 16-bit
Static Devices
32-bit
Static Device
D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7
D8–D15 – D8–D15 D8–D15 D8–D15 D8–15 D8–15
D16–D23 – – – D16–D23 D16–D23 D16–D23
D24–D31 – – – D24–D31 D24–D31 D24–D31
A0/NBS0 A0 – NLB – NLB
(3)
BE0
(5)
A1/NWR2/NBS2 A1 A0 A0 WE
(2)
NLB
(4)
BE2
(5)
A2–A22 A[2:22] A[1:21] A[1:21] A[0:20] A[0:20] A[0:20]
A23–A25 A[23:25] A[22:24] A[22:24] A[21:23] A[21:23] A[21:23]
NCS0 CS CS CS CS CS CS
NCS1/SDCS CS CS CS CS CS CS
NCS2 CS CS CS CS CS CS
NCS3/NANDCS CS CS CS CS CS CS
NCS4/CFCS0 CS CS CS CS CS CS
NCS5/CFCS1 CS CS CS CS CS CS
NCS6 CS CS CS CS CS CS
NCS7 CS CS CS CS CS CS
NRD/CFOE OE OE OE OE OE OE