Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 129
SAM9G20
Figure 19-1: Organization of the External Bus Interface
External Bus Interface
D[15:0]
A[15:2], A[20:18]
PIO
MUX
Logic
User Interface
Chip Select
Assignor
Static
Memory
Controller
SDRAM
Controller
Bus Matrix
APB
AHB
Address Decoders
A16/BA0
A0/NBS0
A1/NWR2/NBS2
A17/BA1
NCS0
NCS3/NANDCS
NRD/CFOE
NCS1/SDCS
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS
CAS
SDWE
D[31:16]
A[24:23]
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
NCS2, NCS6, NCS7
CFCE1
CFCE2
NWAIT
SDA10
NANDOE
NANDWE
NAND Flash
Logic
CompactFlash
Logic
ECC
Controller
A21/NANDALE
A22/NANDCLE